Nonphotolithographic nanoscale memory density prospects

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations

A Linear Logic Programming Language for Concurrent Programming over Graph Structures

We have designed a new logic programming language called LM (Linear Meld) for programming graph-based algorithms in a declarative fashion. Our language is based on linear logic, an expressive logical system where logical facts can be consumed. Because LM integrates both classical and linear logic, LM tends to be more expressive than other logic programming languages. LM programs are naturally concurrent because facts are partitioned by nodes of a graph data structure. Computation is performed at the node level while communication happens between connected nodes. In this paper, we present the syntax and operational semantics of our language and illustrate its use through a number of examples.Comment: ICLP 2014, TPLP 201

SOMA A Tool for Synthesizing and Optimizing Memory Accesses in ASICs

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance

A distributed self-reconfiguration algorithm for cylindrical lattice-based modular robots

International audienceModular self-reconfigurable robots are composed of independent connected modules which can self-rearrange their connectivity using processing, communication and motion capabilities, in order to change the overall robot structure. In this paper, we consider rolling cylindrical modules arranged in a two-dimensional vertical hexagonal lattice. We propose a parallel, asynchronous and fully decentralized distributed algorithm to self-reconfigure robots from an initial configuration to a goal one. We evaluate our algorithm on the millimeter-scale cylindrical robots, developed in the Claytronics project, through simulation of large ensembles composed of up to ten thousand modules. We show the effectiveness of our algorithm and study its performance in terms of communications, movements and execution time. Our observations indicate that the number of communications, the number of movements and the execution time of our algorithm is highly predictable. Furthermore, we observe execution times that are linear in the size of the goal shape

Factors Influencing the Performance of a CPU-RFU Hybrid Architecture

Em face da acentuada revalorização da textualidade nas poéticas da década de 1960 em Portugal – perspectiva que, com algumas especificidades, também se verifica no contexto francês e espanhol –, a demarcação dos poetas emergentes na década seguinte é, por vezes, fortemente reactiva. Mas haverá uma diferença essencial entre estas duas inflexões, corporizadas em poéticas aparentemente distintas? E haverá algum momento, na segunda metade do século XX, em que efectivamente se concretize uma ruptura? No presente estudo, procura-se mostrar que, mais do que produzir uma ruptura, as poéticas emergentes nos anos sessenta do século XX consolidam uma tradição de modernidade escolhendo a sua vertente mais radical, enquanto as poéticas subsequentes preferem reatar a tradição mais remota da modernidade, em sentido baudelairiano. Apesar de estarmos perante dois diálogos diferentes com a tradição, é possível observar que, em ambos os casos, esta é retomada a um ponto que nos impede de falarmos de ruptura

Publication Notes

This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for non-profit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of the Paris Research Laboratory of Digital Equipment Centre Technique Europe, in Rueil-Malmaison, France; an acknowledgement of the authors and individual contributors to the work; and all applicable portions of the copyright notice. Copying, reproducing, or republishing for any other purpose shall require a license with payment of fee to the Paris Research Laboratory. All rights reserved. ii This note outlines the Life Abstract Machine (LAM), an abstract machine used as an intermediate target for the efficient compilation of LIFE. LAM focuses primarily on the efficient implementation of matching, residuation, and currying of functions. Although the topic is not discussed in this note, LAM also implements lazy unification. LAM should be viewed as an intermediate target for compiling LIFE to a native instruction set for a general purpose processor. Thus, this note presents LAM as an abstract machine along with its instructions. However, we also discuss how LAM would be realized in terms of data structures and basic routines. This should facilitate the implementation of both a LIFE-to-LAM compiler and a LAM-to-native-code compiler. iii Keyword